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| INTEGRATED CIRCUITS DATA SHEET SAA3323 Drive processor for DCC systems Preliminary specification File under Integrated Circuits, IC01 May 1994 Philips Semiconductors Philips Semiconductors Preliminary specification Drive processor for DCC systems FEATURES * Operating supply voltage: 2.7 to 3.6 V * Low power dissipation: 84 mW (typ) * Single chip digital equalizer, tape formatting and error correction * 8-bit flash analog-to-digital converter (ADC) for low symbol error rate * Two switchable Infinite Impulse-Response (IIR) filter sections * 10-tap Finite Impulse-Response (FIR) filter per main data channel, with 8 bit coefficients, identical for all main channels * 10-tap FIR filter for the AUX channel * Analog and digital eye outputs * Interrupt line triggered by internal auxiliary envelope processing e.g. label, counter, and others * Robust programmable digital PLL clock extraction unit * Low power SLEEP mode * Slew rate limited Electromagnetic Compatibility (EMC) friendly output * Digital Compact Cassette (DCC) optimized error correction * Programmable symbol synchronization strategy for tape input data * Microcontroller control of capstan servo possible during playback and recording ORDERING INFORMATION PACKAGE TYPE NUMBER PINS SAA3323H SAA3323GP Note 80 80 PIN POSITION TQFP80(1) QFP80(1) MATERIAL plastic plastic SAA3323 * Frequency and phase regulation of capstan servo during playback * Choice of Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) types for system Random Access Memory (RAM) * Scratch pad RAM for microcontroller in system RAM * Integrated interface for Precision Adaptive Sub-band Coding (PASC) data bus * Three wire microcontroller `L3' interface * Protection against invalid auxiliary data * Seamless joins between recordings. GENERAL DESCRIPTION The SAA3323 performs the drive processor function in the DCC system. This function is built up of digital equalizer, error correction and tape formatting functions. The digital equalizer is intended for use with DCC read amplifiers TDA1318 or TDA1380. The tape formatting and error correction circuit is intended for use with PASC ICs SAA2003 and SAA2013, and write amplifiers TDA1319 or TDA1381. CODE SOT315-1 SOT318-2 1. When using reflow soldering it is recommended that the Dry Packing instructions in the "Quality Reference Pocketbook" are followed. The pocketbook can be ordered using the code 9398 510 34011. May 1994 2 Philips Semiconductors Preliminary specification Drive processor for DCC systems BLOCK DIAGRAM SAA3323 handbook, full pagewidth SAA3323 DIGITALTO-ANALOG CONVERTER ANAEYE RDSYNC RDMUX BIAS Vref(p) Vref(n) PHASE LOCKED LOOP ZERO CROSSING FIR (1) IIR (2) ANALOG TO-DIGITAL CONVERTER TAPE INPUT BUFFER SBDIR SBMCLK SBEF SBDA SBCL SBWS AUXILIARY ENVELOPE DETECTION EQUALIZER MODULE SUB-BAND I 2S INTERFACE INTERNAL DATA BUS TAPE OUTPUT BUFFER TCLOCK WDATA ERROR CORRECTOR RAM INTERFACE CONTROL INTERFACE SPEED URDA RESET SLEEP L3REF L3DATA 8 11 6 MLB761 A11 to A16 L3MODE PINO1 PINO2 OEN D0 to D7 L3INT WEN A0 to A10 (1) FIR = Finite Impulse-Response. (2) IIR = Infinite Impulse-Response. Fig.1 Block diagram. May 1994 3 L3CLK PINI Philips Semiconductors Preliminary specification Drive processor for DCC systems PINNING PIN SYMBOL QFP80 SBWS SBCL SBDA SBDIR SBMCLK URDA L3MODE L3CLK L3DATA L3INT VDD1 VSS1 L3REF RESET SLEEP CLK24 AZCHK MCLK TEST3 ERCOSTAT OEN A10/RAS VDD2 VSS2 D7 D6 D5 D4 D3 D2 D1 VDD7 VSS7 D0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 TQFP80 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 word select for sub-band PASC interface bit clock for sub-band PASC interface data line for sub-band PASC interface direction line for sub-band PASC interface master clock for sub-band PASC interface unreliable data mode line for L3 interface bit clock line for L3 interface serial data line for L3 interface L3 interrupt output digital supply voltage digital ground L3 bus timing reference reset SAA3323 sleep mode selection of SAA3323 24.576 MHz clock input channel 0 and channel 7 azimuth monitor 6.144 MHz clock output TEST3 output; do not connect ERCO status, for symbol error rate measurements output enable for RAM address SRAM; RAS DRAM digital supply voltage digital ground data SRAM data SRAM data SRAM data SRAM data SRAM; data DRAM data SRAM; data DRAM data SRAM; data DRAM digital supply voltage for RAM digital ground for RAM data SRAM; data DRAM address SRAM; address DRAM address SRAM; address DRAM address SRAM; address DRAM address SRAM; address DRAM DESCRIPTION SAA3323 TYPE(1) I/O (1 mA) I/O (1 mA) I/O (1 mA) O (1 mA) I O (1 mA) I I I/O (2 mA) O (1 mA) S S O (1 mA) I I I O (1 mA) O (1 mA) O (1 mA) O (1 mA) O (2 mA) O (2 mA) S S I/O (4 mA) I/O (4 mA) I/O (4 mA) I/O (4 mA) I/O (4 mA) I/O (4 mA) I/O (4 mA) S S I/O (4 mA) O (2 mA) O (2 mA) O (2 mA) O (2 mA) May 1994 4 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 PIN SYMBOL QFP80 A4 VSS3 VDD3 A5 A6 A7 A12/PINO5 A14/PINO1 A16/PINO3 A15/PINO4 WEN A13/PINO2 A8 VDD4 VSS4 A9/CAS A11 SPEED PINO2 WDATA TCLOCK VSS5 VDD5 TEST2 RDMUX Vref(p) Vref(n) SUBSTR BIAS VSSA VDDA ANAEYE RDSYNC VDD6 VSS6 CHTST1 CHTST2 TEST0 TEST1 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 TQFP80 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 address SRAM; address DRAM digital ground digital supply voltage address SRAM; address DRAM address SRAM; address DRAM address SRAM; address DRAM address SRAM; Port expander output 5 address SRAM; Port expander output 1 address SRAM; Port expander output 3 address SRAM; Port expander output 4 write enable for RAM address SRAM; Port expander output 2 address SRAM; address DRAM digital supply voltage digital ground address SRAM; CAS for DRAM address SRAM Port expander output 2 serial output to write amplifier 3.072 MHz clock output for tape I/O digital ground digital supply voltage TEST mode select; do not connect analog multiplexed input from read amplifier ADC positive reference voltage ADC negative reference voltage substrate connection bias current for ADC analog ground analog supply voltage analog eye pattern output synchronization output for read amplifier digital supply voltage digital ground channel test pin 1 channel test pin 2 TEST mode select; do not connect TEST mode select; do not connect DESCRIPTION TYPE(1) O (2 mA) S S O (2 mA) O (2 mA) O (2 mA) O (2 mA) O (2 mA) O (2 mA) O (2 mA) O (2 mA) O (2 mA) O (2 mA) S S O (2 mA) O (2 mA) Ot (1 mA) O (1 mA) O (1 mA) S S Ipd IA IA IA IA IA S S OA O (1 mA) S S O (1 mA) O (1 mA) Ipd Ipd Pulse Width Modulation (PWM) capstan control output for deck Ot (1 mA) May 1994 5 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 PIN SYMBOL QFP80 PINI PINO1 SBEF Note 78 79 80 TQFP80 76 77 78 Port expander input Port expander output 1 sub-band PASC error flag line I DESCRIPTION TYPE(1) O (1 mA) O (1 mA) 1. I = input; IA = analog input; Ipd = input with pull-down resistance; I/O = bidirectional; O = output; OA = analog output; Ot = 3-state output; S = supply. RDSYNC ANAEYE CHTST2 CHTST1 64 SUBSTR PINO1 handbook, full pagewidth 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 BIAS PINI 63 62 SBDA SBDIR SBMCLK URDA L3MODE L3CLK L3DATA L3INT V DD1 V SS1 L3REF RESET SLEEP CLK24 AZCHK MCLK TEST3 ERCOSTAT OEN A10/RAS 1 2 3 4 5 6 7 8 9 10 61 60 59 58 57 56 55 54 53 52 51 RDMUX TEST1 TEST0 Vref(n) SBWS SBCL SBEF Vref(p) VDDA V DD6 V SS6 V SSA TEST2 VDD5 VSS5 TCLOCK WDATA PINO2 SPEED A11 A9/CAS VSS4 V DD4 A8 A13/PINO2 WEN A15/PINO4 A16/PINO3 A14/PINO1 A12/PINO5 A7 A6 SAA3323 11 12 13 14 15 16 17 18 19 20 24 25 26 27 29 30 31 32 35 36 37 38 39 21 22 23 28 A0 33 A1 34 40 A5 50 49 48 47 46 45 44 43 42 41 D1 A2 A3 A4 V SS3 V DD2 V DD7 VDD3 D5 VSS2 D6 D4 D3 D7 D2 D0 Fig.2 Pin configuration (SOT315-1; TQFP80). May 1994 6 V SS7 MLB762 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 71 RDSYNC 66 SUBSTR 70 ANAEYE 75 CHTST2 74 CHTST1 77 TEST1 76 TEST0 handbook, full pagewidth 65 Vref(n) 79 PINO1 72 V DD6 69 VDDA 68 V SSA 80 SBEF 73 V SS6 67 BIAS 78 PINI SBWS SBCL SBDA SBDIR SBMCLK URDA L3MODE L3CLK L3DATA L3INT 1 2 3 4 5 6 7 8 9 10 64 63 62 61 60 59 58 57 Vref(p) RDMUX TEST2 VDD5 V SS5 TCLOCK WDATA PINO2 56 SPEED 55 54 53 A11 A9/CAS V SS4 V DD4 A8 A13/PINO2 WEN A15/PINO4 A16/PINO3 A14/PINO1 A12/PINO5 A7 A6 A5 V DD3 MLB763 V DD1 11 VSS1 12 L3REF RESET SLEEP CLK24 AZCHK MCLK TEST3 ERCOSTAT OEN A10/RAS V DD2 V SS2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A1 36 37 38 39 40 V SS3 SAA3323 52 51 50 49 48 47 46 45 44 43 42 41 D2 D1 D7 D6 D5 D4 D3 D0 V DD7 V SS7 A0 A2 A3 Fig.3 Pin configuration (SOT318-2; QFP80). May 1994 7 A4 handbook, full pagewidth May 1994 L analog output R baseband I 2S L analog input R ADC SAA7366 filtered I2 S ADAS3 SAA2013 ADAPTIVE ALLOCATION IEC958 DIGITAL AUDIO I/O TDA1315 search data analog CC L output analog CC R output SFC3 SAA2003 STEREO FILTER CODEC DAC TDA1305 sub-band 2 IS WRAMP TDA1381 WRITE AMP. FIXED HEAD RDAMP TDA1380 READ AMP. RAM 41464 BUFFER 64K x 4 speed control CAPSTAN DRIVE DRP SAA2023 OR SAA3323 DRIVE PROCESSOR TAPE FUNCTIONAL DESCRIPTION Philips Semiconductors Drive processor for DCC systems 8 AUDIO IN/OUT MECHANICS DRIVERS PASC PROCESSOR TAPE DRIVE PROCESSING detect switch SYSTEM MICROCONTROLLER Preliminary specification SYSTEM CONTROL MBD620 SAA3323 Fig.4 DCC system block diagram. Philips Semiconductors Preliminary specification Drive processor for DCC systems A simplified block diagram of the SAA3323 is shown in Fig.1. DCC drive processing The SAA3323 provides the following functions for the DCC drive processing. PLAYBACK MODES * Analog-to-digital conversion * Tape channel equalization * Tape channel data and clock recovery * 10-to-8 demodulation * Data placement in system RAM * C1 and C2 error correction decoding * Interfacing to sub-band serial PASC interface * Interfacing to microcontroller for SYSINFO and AUX data * Capstan control for tape deck. RECORD MODES * Interfacing to sub-band serial PASC interface * C1 and C2 error correction encoding * Formatting for tape transfer * 8-to-10 modulation * Interfacing to microcontroller for SYSINFO and AUX data * Capstan control for tape deck, programmable by microcontroller. SEARCH MODE * Detection and interpretation of AUX envelope information * AUX envelope counting * Search speed estimation. Tape Formatting and Error (TFE) correction module The TFE module has 3 basic modes of operation as shown in Table 1. Table 1 MODE DPAP DPAR DRAR Basic modes of TFE module. SAA3323 EXPLANATION audio and SYSINFO (main data) play; AUX play audio and SYSINFO (main data) play; AUX record audio and SYSINFO (main data) record; AUX record TFE REGISTERS The TFE module has 8 writable and 5 readable registers that are accessible via the L3 interface, one write register (CMD) and four read registers (STATUS0 to STATUS3) which are directly addressable, the other registers are indirectly addressable via commands sent to the CMD register. The registers are named as shown in Table 2. Table 2 TFE register names. READ/WRITE W R R R R W W W W W W W R REGISTER NAME CMD STATUS0 STATUS1 STATUS2 STATUS3 SET0 SET1 SET2 SET3(1) SPDDTY BYTCNT RACCNT SPEED Note 1. The 4 LSBs of register `SET3' set RAM type (RType) and RAM timing (RTim). See Table 3. For normal operation the 4 MSBs of register `SET3' should be logic 0. May 1994 9 Philips Semiconductors Preliminary specification Drive processor for DCC systems Table 3 RAM settings by register SET3. RAM RTYPE 0 RTYPE 1 RTim 0 RTim 1 TFE DATA STREAMS The TFE module has three read/write data streams that are accessible via the L3 interface and they are shown in Table 4. Table 5 TFE commands. COMMAND BYTE NAME 7 RDSPEED LDSET0 LDSET1 LDSET2 LDSET3 LDSPDDTY LDBYTCNT LDRACCNT RDAUX RDSYS RDDRAC RDWDRAC WRAUX WRSYS WRDRAC WRWDRAC Digital equalizer module The digital equalizer module has 2 basic modes of operation as shown in Table 6. Table 6 Basic modes of equalizer module. EXPLANATION main data and AUX channels are equalized only AUX channel is processed; AUX envelope information is processed 0 0 0 0 0 0 0 0 0 0 Y Y 0 0 Y Y 6 0 0 0 0 0 0 0 0 0 0 Z Z 0 0 Z Z 5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 1 0 1 read SPEED register load new TFE settings register 0 load new TFE settings register 1 load new TFE settings register 2 load new TFE settings register 3 load SPDDTY register load BYTCNT register load RACCNT register read AUXILIARY information read SYSINFO EXPLANATION REGISTER SET3 bit 0 bit 1 bit 2 bit 3 TFE `COMMANDS' Table 4 TFE data streams. SAA3323 DATA STREAM NAME SYSINFO AUXINFO Scratch pad RAM READ/WRITE R/W R/W R/W These are the commands that need to be sent to the TFE in order to access the indirectly accessible registers and the data streams, see Table 5. read RAM data bytes (8 bits) from quarter YZ read RAM data words (12 bits) from quarter YZ write AUXILIARY information write SYSINFO write RAM data bytes (8 bits) to quarter YZ write RAM data words (12 bits) to quarter YZ DIGITAL EQUALIZER REGISTERS The digital equalizer module has 9 write only, 3 read only and 1 read/write register(s) that are accessible via the L3 interface, one write register (CMD) and 2 read registers (STATUS0 and STATUS1) which are directly addressable, the other registers are indirectly addressable via commands sent to the CMD register. The registers are named as shown in Table 7. MODE Play Search May 1994 10 Philips Semiconductors Preliminary specification Drive processor for DCC systems Table 7 Digital equalizer register names. READ/WRITE W R R W W W W W R/W R W W W Digital equalizer commands. COMMAND BYTE NAME 7 WRCOEF RDCOEF LDCOEFCNT LDFCTRL LDT1SEL LDT2SEL LDTAEYE LDAEC RDAEC RDSSPD LDINTMSK LDDEQ3SET LDCLKSET 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 1 0 0 0 0 0 0 1 1 0 0 0 4 1 0 1 1 1 1 1 1 0 0 1 1 1 3 0 0 0 0 0 0 1 1 0 0 0 0 0 2 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 EXPLANATION DATA STREAMS SAA3323 REGISTER NAME CMD STATUS0 STATUS1 COEFCNT FCTRL CHT1SEL CHT2SEL ANAEYE AEC SSPD INTMASK DEQ2SET CLKSET Table 9 The digital equalizer module has one write only and one read only data stream that are accessible via the L3 interface and they are shown in Table 8. Table 8 Digital equalizer data streams. DATA STREAM NAME FIR coefficients to buffer bank FIR coefficients from active bank DIGITAL EQUALIZER "COMMANDS" These are the commands that need to be sent to the digital equalizer in order to access the indirectly accessible registers and the data streams. READ/WRITE W W write FIR coefficients to the digital equalizer buffer bank read FIR coefficients from the digital equalizer active bank load FIR coefficient counter load filter control register load CHTST1 pin selection register load CHTST2 pin selection register load ANAEYE channel selection register load AEC counter read AEC counter read SEARCH speed register load interrupt mask register load digital equalizer settings register load PLL clock extraction settings register Table 10 Filter control register. BIT Meaning Default Note 1. CS is a microcontroller controlled coefficient bank switch. This causes the filter coefficients to be activated at a time that is safe for the digital equalizer, i.e. at the end of the FIR program and that the complete value of coefficient number 9 has been received. May 1994 11 7 - 0 6 - 0 5 - 0 4 CS(1) 0 3 SH1 1 2 SH0 0 1 1 Reserved 1 0 Philips Semiconductors Preliminary specification Drive processor for DCC systems Table 11 SH1 and SH2 (FIR output scaling). SH EFFECT ON FIR OUTPUT 1 0 0 1 1 0 0 1 0 1 FIR mod 256 FIR --------- mod 256 2 FIR --------- mod 256 4 FIR --------- mod 256 8 SAA3323 There are 2 banks of coefficients for both the aux and the main data channels, namely the `buffer', and the `active' banks. The microcontroller writes only to the `buffer' banks, and reads only from the `active' banks. The microcontroller can poll the digital equalizer status bit BKSW to see when the switch occurs. BKSW starts life LOW, goes HIGH as a result of the bank switching and goes LOW as result of the complete value of a main data coefficient being received by the digital equalizer. The microcontroller sets CS HIGH before sending the new set of aux or main data coefficients, the digital equalizer resets it once the bank switch occurs. The actual FIR coefficients that are used are a function of the tape head, read amplifier and type of tape (i.e. pre-recorded or own recorded) used, such information is outside of the scope of this data sheet. Transfer of FIR coefficients For the main data channels (tracks 0 to 7) there are 10 coefficients (taps) each of 8 bits, where all of the data channels make use of the same coefficients. The addresses for the main data coefficients 0 to 9 are 0 to 9dec respectively. There are ten coefficients (taps) each of 8 bits for the aux channel (CHAUX). The addresses for the auxiliary coefficients 0 to 9 are 16 to 25dec respectively. Table 12 Coefficient address counter. BIT Meaning Default 7 - 0 6 - 0 5 - 0 Coefficient address counter (COEFCNT) This 5 bit counter is used to point to the FIR coefficient to be transferred to or from the digital equalizer. 4 CC4 0 3 CC3 0 2 CC2 0 1 CC1 0 0 CC0 0 Pin explanations and interfacing to other hardware RESET This is an active HIGH input which resets the SAA3323 and brings it into its default mode, DPAP. This reset does not affect the contents of the FIR filter coefficients in the digital equalizer. This should be connected to the system reset, which can be driven by the microcontroller. The duration of the reset pulse should be at least 15 s. SLEEP This pin is an active HIGH input which puts the SAA3323 in a low power consumption SLEEP mode. This pin should be connected to the DCC SLEEP signal, which can be driven by the microcontroller. The CLK24 clock may be stopped and the VREFP and VREFN inputs brought to ground while the SAA3323 is in `sleep' mode to further reduce power consumption. When recovering from sleep mode, the SLEEP pin should be taken LOW and the SAA3323 reset. CLK24 This is the 24.576 MHz clock input and should be connected directly to the SAA2003 (pin CLK24). Sub-band serial PASC interface connections The timing for the sub-band serial PASC interface is given in Figs 5 to 7. May 1994 12 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full SBCL(in) pagewidth SBWS(in) SBDA(in) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SBCL(in) SBWS(in) SBDA(in) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit number SBCL(in) V IH VOH V IH VOH V IH VOH 2 x t MCLK 40 ns 40 ns MGB381 SBWS(in) SBDA(in) Fig.5 Sub-band serial PASC interface timing; DRAR mode. May 1994 13 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth SBCL(out) SBWS(out) SBDA(out) SBEF(out) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SBCL(out) SBWS(out) SBDA(out) SBEF(out) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit number SBMCLK(in) V IH V IL VOH V OL 60 ns VOH V OL VOH V OL 7 ns VOH V OL 7 ns MGB382 SBCL(out) SBWS(out) SBDA(out) SBDA(out) Fig.6 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 1. May 1994 14 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth SBCL(in) SBWS(in) SBDA(out) SBEF(out) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SBCL(in) SBWS(in) SBDA(out) SBEF(out) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit number SBCL(in) V IH V IL V IH V IL 2 x t MCLK 40 ns 40 ns VOH VOL (40 85) ns VOH VOL (40 40) ns MGB383 SBWS(in) SBDA(out) t MCLK SBDA(out) t MCLK Fig.7 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 0. SBMCLK This is the sub-band master clock input for the sub-band serial PASC interface. The frequency of this signal is nominally 6.144 MHz. When the SAA3323 is used with SAA2003 this pin is tied to ground, and the TFE settings bit `DRPMAS' set to logic 1. SBDIR This output pin is the sub-band serial PASC bus direction signal, it indicates the direction of transfer on the sub-band serial PASC bus. This pin connects directly to the SBDIR pin on the SAA2003. The transfer directions are shown in Table 13. Table 13 PASC bus transfer directions. SBDIR 1 0 DIRECTION SAA3323 to SAA2003 transfer (audio play) SAA2003 to SAA3323 transfer (audio record) SBCL This input/output pin is the bit clock line for the sub-band serial PASC interface to the SAA2003. When used with SAA2003 this pin is input only. It has a nominal frequency of 768 kHz. SBWS This input/output pin is the word select line for the sub-band serial PASC interface to the SAA2003. When used with SAA2003 this pin is input only. It has a nominal frequency of 12 kHz. SBDA This input/output pin is the serial data line for the sub-band serial PASC interface to the SAA2003. SBEF This active HIGH output pin is the error-per-byte line for the sub-band serial PASC interface to the SAA2003. 15 May 1994 Philips Semiconductors Preliminary specification Drive processor for DCC systems URDA This active HIGH output pin indicates that the main data (audio), the SYSINFO and the AUXILIARY data are NOT usable, regardless of the state of the corresponding reliability flags. The state of this pin is reflected in the URDA bit of STATUS byte 0, which can be read by the microcontroller. This pin should be connected directly to SAA3323 the URDA pin of the SAA2003. URDA goes active as a result of a reset, a mode change from mode DRAR to DPAP, or if the SAA3323 has had to re-synchronize with the incoming data from tape. The position of the first sub-band serial PASC bytes in a tape frame is shown in Figs 8 and 9. handbook, full pagewidth SNUM 0 1 SBWS L3REF 'FIRST BYTE" SBDA MGB384 byte 0 byte 1 byte 2 Fig.8 Position of first sub-band serial PASC bytes in a tape frame in DPAP/DPAR mode. handbook, full pagewidth SNUM 3 0 SBWS L3REF 'FIRST BYTE' SBDA MGB385 byte 0 byte 1 byte 2 Fig.9 Position of first sub-band serial PASC bytes in a tape frame in DRAR mode. May 1994 16 Philips Semiconductors Preliminary specification Drive processor for DCC systems RAM connections The SAA3323 has been designed to operate with DRAMs and SRAMs. Suitable DRAMs are 64K x 4-bit or 256K x 4-bit configurations operating in page mode, with an access time of 80 to 100 ns. The timing for read, write and refresh cycles for DRAMs is shown in Figs 10 to 12. The timing for SRAMs is shown in Figs 13 to 19. For fast SRAMs: (these values are subject to verification during characterization in). The conditions (most critical at the required VDD) are shown in Table 14. Table 14 Fast SRAM conditions. CONDITION(1) Write pulse duration Data set-up to rising WEN Write cycle time Read access time Note 1. The SAA3323 should work in: RType = `01'; RTim = `00' mode. A9/CAS When SAA3323 is used with SRAM this output pin is Address line 9, and should be connected directly to the corresponding address pin on the SRAM. When SAA3323 is used with DRAM this output pin is the column address strobe (active LOW), it connects directly to the column address strobe pin of the DRAM. A10/RAS When SAA3323 is used with SRAM this output pin is Address line 10, and should be connected to the corresponding address pin of the SRAM. When SAA3323 is used with DRAM this output pin is the row address strobe (active LOW), it connects directly to the row address strobe pin of the DRAM. TIME tW 140 ns tsu 72 ns Tcy 200 ns tACC 240 ns OEN SAA3323 This output pin is the output enable (active LOW) for the RAM, it connects directly to the output enable pin of the RAM. WEN This output pin is the write enable (active LOW) for the RAM, it connects directly to the write enable pin of the RAM. A0 TO A8 When SAA3323 is used with DRAM these output pins are the multiplexed column and row address lines. When the 64K x 4-bit DRAM is used, pins A0 to A7 should be connected to the DRAM address input pins, and pin A8 should be left unconnected. When using the 256K x 4-bit DRAM the address pins A0 to A8 should be connected to the address input pins of the DRAM. When SAA3323 is used with SRAM these are the lower address pins and should be connected directly to the SRAM address pins. A11 This output pin is the an address pin for the SRAM and when SRAM is used they should be connected directly to the address pins of the SRAM. When DRAM is used this pin should not be connected. A10 AND A12 TO A16 These output pins are the upper address pins for the SRAM and when SRAM is used they should be connected directly to the address pins of the SRAM. When DRAM is used or when the small SRAM is used all or some of these pins become available as Port expander outputs. May 1994 17 Philips Semiconductors Preliminary specification Drive processor for DCC systems Table 15 Port expander outputs. PIN PIN NAME QFP80 A14/PINO1 A13/PINO2 A16/PINO3 A15/PINO4 A12/PINO5 D0 TO D3 46 50 47 48 45 TQFP80 44 48 45 46 43 PORT EXPANDER OUTPUT PINO1 PINO2 PINO3 PINO4 PINO5 RType = 00 RType = 00 SAA3323 CONDITIONS RType = 00 or RType = 01 RType = 00 or RType = 01 RType = 00 When SAA3323 is used with SRAM these I/O pins form the lower nibble of the data bus connection to the RAM, and should be connected to the corresponding data I/O pins of the SRAM. When SAA3323 is used with DRAM these input/output pins are the data lines for the RAM, they should be connected directly to the DRAM data I/O pins. D4 TO D7 These input/output pins are the upper nibble of the data bus for use with SRAM, and when SRAM is being used they should be connected directly to the corresponding SRAM I/O pins. handbook, full pagewidth WEN OEN t RAS A10/RAS A9/CAS A0 to A8 D0 to D3 ,,,, ,,,, ,,,, ,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,, ,,,, , , t ASC t ASR t RAH t CAH t CP ROW ADDRESS COLUMN ADDRESS t CAC COLUMN ADDRESS COLUMN ADDRESS t OFF t OEZ NIBBLE 0 DATA NIBBLE 1 DATA NIBBLE 2 DATA t RAC t RP t RCD t CAS MGB386 Fig.10 DRAM read cycle timing. May 1994 18 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth t WCS t WCH WEN OEN t RAS A10/RAS A9/CAS A0 to A8 D0 to D3 ,,,,, ,,,, ,,,, ,,,,, ,,,,, ,,,, ,,,, ,,,,, ,,,, ,,,,, ,,,, t ASC t ASR t RAH t CAH t CP ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS NIBBLE 0 DATA t DH NIBBLE 1 DATA NIBBLE 2 DATA t DS t RP t RCD t CAS MGB387 Fig.11 DRAM write cycle timing. handbook, full pagewidth WEN OEN t RP A10/RAS t RAS A9/CAS A0 to A8 ,,,, t ASR t RAH ROW ADDRESS MGB388 D0 to D3 Fig.12 DRAM refresh cycle timing. May 1994 19 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth WEN OEN A0 to A16 D0 to D7 ,,, ,,,, ,,,, ,,,,,, ,,,,,,,,,,,,,, ,,,,,,, ,, , ,, ,,,, , ,,,,, ADDRESS t AA ADDRESS t OH t OHZ DATA DATA t OLZ MGB389 READ READ Fig.13 Fast SRAM read cycle timing. handbook, full pagewidth t WP t WP WEN OEN A0 to A16 D0 to D7 ,,,,,,,,,, ,,,,,,, ,,,,, ,, ,,, ,,,,,, , ,,, tAW t WC ADDRESS ADDRESS t DW1 t OLZ t DHO1 t DW2 DATA DATA DATA t DH1 tAA MGB390 t OHZ t DH2 WRITE READ MODIFY WRITE Fig.14 Fast SRAM write cycle timing; RTim = "00". May 1994 20 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth t WP WEN t WP OEN A0 to A16 D0 to D7 ,,, ,,,,,, ,,, ,,,,, ,,,,,,, ,, ,, ,,,,, ,, tAW t WC ADDRESS t DAH t DW1 ADDRESS t DHO1 t OLZ t DW2 DATA t DAH DATA DATA t DDH tAA MGB391 t OHZ t DDH WRITE READ MODIFY WRITE Fig.15 Fast SRAM write cycle timing; RTim = "01". handbook, full pagewidth t WP t WP WEN OEN A0 to A16 D0 to D7 ,, ,,,,,, ,,,, ,,,,, ,, ,,,,,, ,,,, ,,,,, ,,,,,, ,, ,,, tAW t WC ADDRESS ADDRESS t DW1 t OLZ t DHO1 t DW2 DATA DATA DATA t DH1 tAA t OHZ t DH2 MGB392 t WOA WRITE READ MODIFY WRITE Fig.16 Fast SRAM write cycle timing; RTim = "10". May 1994 21 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth WEN OEN A0 to A16 D0 to D7 ,,, ,,,,,, ,,, ,,, ,,,,, ,,, ,,,, ,,, ,,, ,,,, MGB393 WRITE READ MODIFY WRITE Fig.17 Fast SRAM write cycle timing; RTim = "11". handbook, full pagewidthWEN OEN A0 to A16 D0 to D7 ,, ,,,, ,,,,, ,,,,,, , ,, ,,,,, ,, , ,,, ,, ADDRESS ADDRESS t OLZ t OHZ DATA DATA t AA t OH MGB394 READ READ Fig.18 Slow SRAM read cycle timing. May 1994 22 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth t WP WEN t WP OEN A0 to A16 D0 to D7 ,,, ,,,, ,,,, ,,,,,, ,,,, ,,,, ,,,, ,,,, t AW t WC t AW t WC ADDRESS ADDRESS t DW2 t DW1 DATA DATA t DH t DH MGB395 WRITE WRITE Fig.19 Slow SRAM write cycle timing. Table 16 Timing values for Figs 10 to 12. SYMBOL tRP tRAS tRCD tCP tCAS tASR tRAH tASC tCAM tDS tDH tWCS tWCH tRAC tCAC 110 510 70 30 100 100 25 30 100 25 100 30 100 160 80 VALUE (ns) Table 17 Timing values for Figs 13 to 17. SYMBOL tWP tAW tWC tDW tDM tAA tHC 140 180 200 72 25 240 250 VALUE (ns) Table 18 Timing values for Figs 18 and 19. SYMBOL tWP tAW tWC tDW tDM tAA 225 260 300 140 25 280 VALUE (ns) May 1994 23 Philips Semiconductors Preliminary specification Drive processor for DCC systems Read/write connections TCLOCK This output pin is the 3.072 MHz clock output for the read and write amplifiers, it should be connected directly to the WCLOCK pin of the write amplifier and to the RDCLK pin of the read amplifier. RDMUX This input pin carries the time multiplexed analog tape channel signals from the read amplifier. Vref(n) AND Vref(p) These are the lower and upper voltage reference inputs for the ADC in the digital equalizer part of SAA3323. BIAS This pin defines a bias current for the ADC. It should be connected to the analog supply voltage VDDA via a 47 k resistor. RDSYNC SAA3323 This output line provides synchronization information for the read Amplifier data transfers. The relationship between TCLOCK, RDSYNC and the channel information carried by the RDMUX line is given in Fig.20. This pin should be connected directly to the RDSYNC pin of the read amplifier. When the digital equalizer in SAA3323 is in search mode this pin will be HIGH ensuring that only the AUX channel is processed by the SAA3323. WDATA This output pin is the multiplexed data and control line for the write amplifier. Figure 21 shows the manner in which this information is multiplexed onto WDATA. The WDATA pin should be connected directly to the WDATA pin of the write amplifier. T handbook, full pagewidth CLOCK RDMUX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AUX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AUX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AUX MGB396 RDSYNC Fig.20 RDMUX, RDSYNC and TCLOCK timing. TCLOCK handbook, full pagewidth WDATA TCH0 TCH1 TCH2 TCH3 TCH4 TCH5 TCH6 TDAPLB TAUPLB SYNC TCHAUX TERAUX TCH7 MGB397 Fig.21 WDATA and TCLOCK timing. May 1994 24 Philips Semiconductors Preliminary specification Drive processor for DCC systems Tape deck capstan control connections SPEED This pin outputs a pulse width modulated signal that may be used for controlling the tape capstan of the deck. SAA3323 Operation of the SPEED control signal Table 19 gives the sources that determine the duty factor of the SPEED signal. Note that the 3-state SPEED output may be put into high-impedance state by programming the TFE setting by bit HiZSpd. Table 19 SPEED signal duty factor. MODE DPAP DPAP DPAR DPAR DRAR DRAR Notes 1. "Tape" means that the duty factor has been calculated from the played back main data tape signal. When tape is the source for the duty factor of the SPEED signal, the type of regulation can be chosen with the TFE settings bits EnFReg and SeINBand. 2. "C" means that the microcontroller programs the duty factor via the SPDDTY register. 3. "50%" means that the duty factor is fixed at 50%. CSPD 0 1 0 1 0 1 SOURCE FOR SPEED DUTY FACTOR tape(1) C(2) tape(1) C(2) 50%(3) C(2) May 1994 25 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 MEA717 100 % 91 % duty factor speed 50 % 9% 0 + 2 blocks + 10.6 ms + 1.65 blocks + 8.8 ms 0 - 1.65 blocks - 8.8 ms - 2 blocks - 10.6 ms Fig.22 SPEED regulation duty factor as a function of phase characteristic. If EnFReg is programmed `LOW' then there is phase regulation of the capstan speed. The period of the pulse width modulated SPEED signal is 41.66 s. The SAA3323 performs a new calculation to determine the duty factor of SPEED once every 21.33 ms, giving a sampling rate of approximately 46.9 Hz. This calculation is basically a phase comparison between the incoming Main Data tape frame and an internally generated reference. The SPEED duty factor as a function of phase characteristic is shown in Fig.22. As shown the duty factor increases monotonously from approximately 9% when the incoming Main Data tape frame is 1.65 tape blocks (8.8 ms) too early up to 91% when it is 1.65 tape blocks (8.8 ms) too late. Outside of a 2 tape blocks range the pulse width characteristic overflows and repeats itself forming a sawtooth pattern. The SAA3323 has an internal buffer of 8.8 ms outside of which the phase information is invalid. Table 20 POT and FOT deviation thresholds. SeINBand 0 1 If EnFReg is programmed `HIGH' then the above description is over-ridden with frequency information. If the incoming main data bit rate deviation from the nominal 96000 bits/s rate is less than the Phase Only Threshold (POT) then the control is as described above in the phase control description. If the deviation is more than the Frequency Only Threshold (FOT) then the SPEED information is gated with the phase information resulting in the SPEED signal being continuously HIGH or LOW while the condition continues. If the deviation is between the POT and the FOT then the frequency information is gated with the Phase information for 50% of the time. The deviation thresholds POT and FOT are programmable via the TFE settings bit SeINBand. POT (DEVIATION FROM NOMINAL) 6% 3% FOT (DEVIATION FROM NOMINAL) 9% 4.5% May 1994 26 Philips Semiconductors Preliminary specification Drive processor for DCC systems If SLEEP is `HIGH' then the state of the SPEED signal will be the state that it was in just before the SAA3323 went into sleep. Thus if SPEED was HIGH just before sleep it will stay HIGH during sleep. The same applies if it was LOW or if it was in `high-Z' state. Note that a reset of the SAA3323 will take the SPEED signals out of `high-Z' state. Microcontroller connections L3REF This active LOW output pin indicates the start of a time segment, it goes LOW for 5.2 s once every 42.66 ms approximately and can be used for generating interrups for the microcontroller. If a re-synchronization occurs then the time between the occurrences van vary. This pin can be connected directly to the interrupt input of the microcontroller. L3CLK This input pin is the clock line for the microcontroller interface. L3DATA This input/output pin is the serial data line for the microcontroller interface. L3MODE This input determines the type of transfer that is occurring between the microcontroller and the SAA3323. If L3MODE is LOW then a device address can be sent by the microcontroller. If L3MODE is HIGH then a data transfer may be occurring. L3INT This pin carries interrupts from the digital equalizer module. It can also be programmed to reflect the state of the AENV, LABEL and VIRGIN signals. Table 21 Timing values for Fig.23. SYMBOL tW1 td1 th2 td2 td5 tcL tcH tsu1 th1 td3 th3 td4 td4(2) Notes TIME(1) SAA3323 T + tsu (L3MODE) + th (L3MODE); tw1 200 ns T + tsu (L3MODE) + th (L3CLK); td1 200 ns T + tsu (L3CLK) + th (L3MODE); th2 200 ns T + tsu (L3CLK) + td (L3DATA); td2 250 ns 0 td5 50 ns T + tsu (L3CLK) + th (L3CLK); tcL 200 ns T + tsu (L3CLK) + th (L3CLK); tcH 200 ns T + tsu (L3DATA) + th (L3CLK); tsu1 200 ns T + tsu (L3CLK) + th (L3DATA); th1 35 ns 2 x T + tsu (L3MODE) + td (L3DATA); td3 250 ns T + th (L3CLK) + td (L3DATA); th3 50 ns 2 x T + tsu (L3CLK) + td (L3DATA); td4 410 ns 3 x T + tsu (L3CLK) + td (L3DATA); td4 575 ns 1. T is the period of the master clock on the chip. 2. td4 is the delay time between the last bit of a byte and first bit of the next byte, if no `halt' is used. May 1994 27 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth t W1 t h2 L3MODE t d1 t d5 L3DATA DRP to microcontroller t d5 L3CLK a. L3MODE t cL L3CLK t d1 L3DATA microcontroller to DRP 0 t su1 t h1 1 2 3 4 5 6 7 t cH t h2 b. L3MODE t cL L3CLK t d1 L3DATA microcontroller to DRP 0 t su1 t cH t h1 1 2 3 4 5 6 7 t h2 c. L3MODE t cL L3CLK t d1 L3DATA DRP to microcontroller 0 t d2 t d3 t d4 t h3 1 2 3 4 5 6 7 MGB398 t cH t h2 t d5 d. a. Halt mode. b. Addressing mode. c. Data mode (transfer from microcontroller to SAA3323). d. Data mode (transfer from SAA3323 to microcontroller). Fig.23 L3 interface timing and typical transfers (1). May 1994 28 handbook, full pagewidth May 1994 L3MODE L3CLK L3DATA TFE3 WCMD LDSET0 TFE3 WDAT SET0 DATA TFE3 WCMD LDSET1 TFE3 WDAT SET1 DATA Philips Semiconductors Drive processor for DCC systems a. L3MODE L3CLK L3DATA TFE3 RSTAT STATUS0 DATA STATUS1 DATA STATUS2 DATA STATUS3 DATA b. L3MODE L3CLK L3DATA TFE3 WCMD LDBYCYNT TFE3 WDAT D8HEX TFE3 WCMD RDSYS TFE3 RDAT SYSINFO(8) SYSINFO(9) 29 L3MODE L3CLK L3DATA TFE3 WCMD LDBYCYNT TFE3 WDAT D8HEX L3MODE L3CLK L3DATA TFE3 RSTAT STATUS0 DATA TFE3 RDAT SYSINFO(9) c. TFE3 WCMD RDSYS TFE3 RSTAT STATUS0 DATA TFE3 RDAT SYSINFO(8) MGB399 d. Preliminary specification a. Write settings bytes 0 and 1 to TFE3 part of SAA3323. b. Read all 4 status bytes from TFE part of SAA3323. c. Read 2 SYSINFO bytes starting at byte 8 (in high-speed transfer part of program). d. Read 2 SYSINFO bytes starting at byte 8 (in low-speed transfer part of program). SAA3323 Fig.24 L3 interface timing and typical transfers (2). Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 test pins TEST0 TO TEST3 These input pins are for test only, do not connect. AZCHK This output pin indicates the occurrence of a tape channel sync symbol on tape channels TCH0 and TCH7, the distance between the pulses for the TCH0 and TCH7 channels gives a measure of the azimuth error between the tape and head alignment. Figure 25 shows the typical timing for this signal. ERCOSTAT This output pin can be connected to a symbol error rate measurement system. Port expansion pins PINI This input pin is connected directly to the PINI bit in the status byte 1, it can be read by the microcontroller, and may be used for any CMOS level compatible input signals. PINO1 SAA3323 This output pin is connected directly to the PINO1 bit of the TFE settings 0 register. The microcontroller can set or reset this pin. PINO2 TO PINO5 Depending upon the type and the size of system RAM used, some or all of these Port expander output pins may be available, (please see Section "RAM connections" "A10 and A12 to A16" on interfacing to the RAM pins). Supply pins VDD1 TO VDD6 These are the supply pins, all of these pins must be connected. We recommend that each power supply pin pair (i.e. VDD1 to VSS1, VDD2 to VSS2, etc.) be decoupled using a 22 nF capacitor as close as is physically possible to the pins of the SAA3323. VSS1 TO VSS6 These are the supply ground pins, all of which must be connected. handbook, full pagewidth Duration of the one tape block 5.3 ms AZCHK (8 periods MCLK) 1.3 s MEA705 This is a measure of the azimuth error. Nominal Inter Frame Gap (IFG) lasts 660 s. Fig.25 AZCHK timing. May 1994 30 Philips Semiconductors Preliminary specification Drive processor for DCC systems VDD7 This is the supply pin for the output buffers to the data lines of the system RAM. It should always be connected externally. Decouple this pin with a 22 nF capacitor to the VSS7 pin. VSS7 This is the ground supply pin for the output buffers of the data lines of the system RAM. This pin is connected Table 22 Interrupt mask register. BIT Meaning Default Notes 1. Vup rising edge of VIRGIN interrupt. 2. AEup rising edge of AUX envelope interrupt. 3. AEdn falling edge of AUX envelope interrupt. 4. Lup rising edge of LABEL interrupt. 5. Ldn falling edge of LABEL interrupt. 6. ECZ AUX envelope counter has just reached zero interrupt. BP1 AND BP0 (BYPASS) If any of the bypass bits are HIGH then the interrupts are not passed on to the microcontroller, instead the level of the corresponding signal is available an the interrupt pin. Table 23 BP1 and BP0. BP EFFECT OF BYPASS 1 0 0 1 1 Notes 1. LAB = LABEL (HIGH if a LABEL condition is detected in the envelope of the AUX channel). 2. AENV = envelope of the AUX channel (1 bit binary). 3. VIR = VIRGIN (indicated by the total [continuous] absence of signal on the AUX channel). 0 0 1 0 1 no bypass LAB on L3INT pin; note 1 AENV on L3INT pin; note 2 VIR on L3INT pin; note 3 MASK 7 BP1 0 6 BP0 0 5 Vup(1) 0 4 AEup(2) 0 3 AEdn(3) 0 2 Lup(4) 0 1 SAA3323 internally to all the supply ground pins (VSS1 to VSS6), however it should always be connected externally. Auxiliary envelope detection INTMASK INTMASK is a interrupt mask register. This register sets the mode of operation for the interrupt interface, and is writable only. 0 ECZ(6) 0 Ldn(5) 0 The AUX envelope information is only valid when the digital equalizer is in search mode and when the tape speed is between the values of 3 to 48 x nominal tape speed. The timing relationships between the AUX channel input signal, AENV, LAB and VIR are shown in Figs 26 to 28. The delays td1 and td2 are between 0.25 and 0.5tAUX (AUX envelope periods). The delays td3, td4, td5 and td6 are between 2 and 6tAUX (AUX envelope periods). When using the digital equalizer in search mode first program the digital equalizer to search mode, then program the INTMASK register. If the BP1 and BP0 bits are LOW then the mask bits take effect. Any combination of the mask bits may be HIGH, enabling the corresponding interrupts. The interrupt pin L3INT is active LOW when used for interrupts and active HIGH when used for bypassing. So if it is not in bypass mode and at least one of the interrupts has occurred it will go LOW and stays LOW until DEQ status byte 0 has been read. Extra interrupts that occur after the first interrupt and before the DEQ status byte 0 is read are seen in the status register. Extra interrupts that occur after the status byte 31 May 1994 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 has been read will generate a new interrupt. Interrupts that are already noted in the digital equalizer Status 0 are cleared by reading it. Table 24 Digital equalizer STATUS0. BIT Meaning Notes 1. BKSW (filter bank switched) indicates that the last main data coefficients sent to the digital equalizer have been activated. 2. Vup indicates whether an interrupt caused by the rising edge of VIRGIN has occurred. 3. AEup indicates whether an interrupt caused by the rising edge of AUX envelope has occurred. 4. AEdn indicates whether an interrupt caused by the falling edge of AUX envelope has occurred 5. Lup indicates whether an interrupt caused by the rising edge of LABEL has occurred. 6. Ldn indicates whether an interrupt caused by the falling edge of LABEL has occurred. 7. ECZ indicates that the AUX envelope counter has reached zero. 7 BKSW(1) 6 TEST 5 Vup(2) 4 AEup(3) 3 AEdn(4) 2 Lup(5) 1 Ldn(6) 0 ECZ(7) handbook, full pagewidth t AUX RDMUX AENV t d1 t d2 MGB400 Fig.26 AUX channel envelope to AENV delays. handbook, full pagewidth t AUX AENV (internal) LAB t d3 t d4 MGB401 Fig.27 AENV to LAB delays. May 1994 32 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth t AUX AENV (internal) Vir t d5 t d6 MGB402 Fig.28 AENV to VIR delays. Table 25 Digital equalizer STATUS1. BIT Meaning Notes 1. VIR gives the state of the VIRGIN signal. 2. AENV represents the state of the AENV signal. 3. LAB gives the state of the LAB signal. 7 - 6 - 5 - 4 - 3 - 2 VIR(1) 1 AENV(2) 0 LAB(3) AUX envelope count (AECNT) register This 16 bit register is used for loading the AUX envelope counter and for reading the state of that counter, it is therefore readable and writable as 2 bytes. Least Significant Byte first. Table 26 AECNT register. AECNT BIT Meaning 7 27 LEAST SIGNIFICANT BYTE 6 26 5 25 4 24 3 23 2 22 1 21 0 20 7 215 MOST SIGNIFICANT BYTE 6 214 5 213 4 212 3 211 2 210 1 29 0 28 Search speed (SSPD) register SR 51.2 Search speed = 2 x ---------- x normal speed SV- Table 27 Search speed register. BIT Meaning Notes 1. SVF speed validation flag, if HIGH then the search speed measurement is invalid. 2. SV4 to SV0 search speed value. 3. SR1 and SR0 search speed range. May 1994 33 7 SVF(1) 6 SV4(2) 5 SV3(2) 4 SV2(2) 3 SV1(2) 2 SV0(2) 1 SR1(3) 0 SR0(3) Philips Semiconductors Preliminary specification Drive processor for DCC systems ANAEYE register Table 28 ANAEYE register analog eye pattern selection register. BIT Meaning Default Notes 7 - 0 6 - 0 5 - 0 4 AEN(1) 0 3 ACHN3(2) 0 2 ACHN2(2) 0 1 SAA3323 0 ACHN0(2) 0 ACHN1(2) 0 1. AEN analog eye pattern output enable. If this bit is LOW the Digital-to-Analog Converter (DAC) is switched off and the output is HIGH. 2. ACHN3 to ACHN0 select channel for analog eye output. Table 29 ACHN3 to ACHN0 channel selections for analog eye output. ACHN CHANNEL ON ANAEYE 3 0 0 0 0 0 0 0 0 1 2 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 1 2 3 4 5 6 7 AUX T1sel register Table 30 T1SEL register CHTST1 pin selection register. BIT Meaning Default 7 - 0 6 T1F2 0 5 T1F1 0 4 T1F0 0 3 T1C3 0 2 T1C2 0 1 T1C1 0 0 T1C0 0 Table 31 T1C3 to T1C0 CHTST1 pin channel selections. T1C CHANNEL ON CHTST1 3 0 0 0 0 0 0 0 0 1 May 1994 2 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 34 0 0 1 0 1 0 1 0 1 0 0 1 2 3 4 5 6 7 AUX Philips Semiconductors Preliminary specification Drive processor for DCC systems Table 32 T1F2 to T1F0 CHTST1 pin function selections. T1F SAA3323 FUNCTION OF CHTST1 PIN 2 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 off; logic 0 digital eye pattern sliced data bit clock clock extraction frequency The digital eye pattern is in 8 bits two's complement notation, the sliced data and the bit clock give the current binary state of the corresponding signals, and the clock extraction frequency output is in 8 bits offset binary format. The timing diagrams for the digital eye pattern output and the clock extraction frequency output are shown in Fig.29. T2sel register Table 33 T2SEL register CHTST2 pin selection register. BIT Meaning Default 7 - 0 6 T2F2 0 5 T2F1 0 4 T2F0 0 3 T2C3 0 2 T2C2 0 1 T2C1 0 0 T2C0 0 Table 34 T2C3 to T2C0 CHTST2 pin channel selections. T2C 3 0 0 0 0 0 0 0 0 1 2 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 CHANNEL ON CHTST2 0 1 2 3 4 5 6 7 AUX Table 35 T2F2 to T2F0 CHTST2 pin function selections. T2F FUNCTION OF CHTST2 PIN 2 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 off; logic 0 digital eye pattern sliced data bit clock clock extraction frequency May 1994 35 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth RDSYNC TCLOCK MCLK LSB CHTST 0 1 2 3 4 5 6 MSB 7 0 1 2 3 MGB403 Fig.29 CHTST1 and CHTST2 output timing. Table 36 DEQSET digital equalizer settings. BIT Meaning Default Note 1. ACup is the AUX envelope counter direction is up. This setting caused the AUX envelope counter increment or to decrement by 1 every rising edge of the AUX envelope signal AENV. 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 ACup(1) 0 1 DM1 0 0 DM0 0 DM1 and DM0 Table 37 DM1 and DM0 digital equalizer mode of operation. DM 1 0 0 1 1 Notes 1. In normal mode the main data channels and the AUX channel are processed (equalized), the AUX channel envelope information is not processed. 2. In search mode only the AUX channel is processed by the digital equalizer. 3. Off means that the digital equalizer is put to sleep (low power), this can be used for example in portable recording equipment. RDSYNC is HIGH if off mode. Also note that the other digital equalizer registers are not addressable while the digital equalizer is in off mode. May 1994 36 0 0 1 0 1 MODE OF OPERATION OF DIGITAL EQUALIZER normal(1) search(2) off(3) off(3) Philips Semiconductors Preliminary specification Drive processor for DCC systems CLKSET Table 38 CLKSET clock extraction settings. BIT Meaning Default Note 7 LEAE(1) 1 6 FR1 0 5 FR0 0 4 GNOR 1 3 GE1 1 2 GE0 0 1 SAA3323 0 RD0 0 RD1 1 1. LEAE (leakage enable): this setting enables a leakage function in the PLL clock extraction loop filter. This gives a slightly improved performance with high SER tapes at the cost of a slight decrease in dynamic performance. For home (static) applications program this bit to logic 1 and for portable applications to logic 0. Table 39 FR1 and FR0 clock extraction frequency range control. FR 1 0 0 1 1 0 0 1 0 1 EFFECT ON PLL FREQUENCY LOOP range 8% range 16% range 22% range 28% Table 40 GNOR gain in normal frequency range mode of clock extraction. GNOR 0 1 EFFECT ON GAIN IN NORMAL RANGE gain 2; for portable (mobile) applications gain 1; for home (static) applications Table 41 GE1 and GE0 gain in extended frequency range mode of clock extraction. GE 1 0 0 1 1 0 0 1 0 1 EFFECT ON PLL GAIN IN EXTENDED RANGE gain 2 gain 3 gain 4 gain 5; do not use Note that in the (FR = 0) range the clock extraction stays in its normal range only, hence it does not enter the extended range. Figure 30 shows the lock characteristic of the clock extraction PLL. MGB404 handbook, full pagewidth 30 bit rate deviation (%) (3) 20 (2) (1) 28% frequency loop range limitation 22% frequency loop range limitation 16% frequency loop range limitation 8% frequency loop range limitation 10 (1) Gain 4. (2) Gain 3. (3) Gain 2. 0 102 10 3 f (Hz) 10 4 Fig.30 Clock extraction PLL lock characteristic. May 1994 37 Philips Semiconductors Preliminary specification Drive processor for DCC systems RD1 and RD0 return delay This is the delay before returning to normal mode after being in `extended range mode' (i.e. the number of consecutive channel clock bit periods where the bit clock frequency falls within the normal range before the clock extraction returns to normal frequency mode). Table 42 RD1 and RD0 return delay. RD 1 0 0 1 1 0 0 1 0 1 DELAY IN BITS TO RETURN TO NORMAL MODE 64 128 256 512 SAA3323 The 128 bytes in each tape frame contain SYSINFO. The SYSINFO bytes can for convenience, be considered as being grouped into 4 SYSINFO blocks with: SYSBLK0 SI0 to SI31, SYSBLK1 SI31 to SI63, etc. In modes DPAP and DRAR SYSINFO transfers may occur in two ways: 1. 4 blocks of 36 bytes, one block being transferred to the SAA3323 in each time segment. 2. 1 block of 128 bytes being transferred in time segment 1. In mode DRAR SYSINFO must be transferred as 4 blocks of 32 bytes, one block in each segment. Figures 31 to 34 show the offsets between the SYSINFO and AUX and the time segment counter, for the various modes of operation of the SAA3323. SYSINFO and AUX data offsets in the SAA3323 AUX data consists of 4 blocks of 36 bytes, one block being transferred in each (n) time segment. Table 43 Block offsets with respect to time segment. MODE DPAP DESCRIPTION SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0; if AUX and main were recorded simultaneously then AUXBLK = (SNUM + 1) MOD4; else read and interpret 1 AUX block in each time segment. SYSBLK = SNUM; AUXBLK = (SNUM + 1) MOD4 SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0 DRAR DPAR May 1994 38 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SNUM 01 1 3 2 0 0 1 2 3 2 3 1 3 0 2 0 1 3 1 2 0 2 3 1 3 0 2 0 1 3 1 2 0 2 3 1 3 0 1 2 2 3 AUX BLK 01 2 3 SYS BLK SYS BLK * ,, ,,,, ,,, ,, ,, ,,,, ,,, ,, 01 0 1 2 3 0 1 2 3 0 1 2 3 01 2 3 0 1 2 3 0 1 2 3 0 1 2 MLB413 AUX, MAIN DATA INPUT FROM TAPE Fig.31 SYSINFO and AUX block delays in DPAP mode; audio and AUX simultaneously recorded. SNUM 01 2 3 0 1 2 3 0 1 2 3 0 1 2 AUX BLK DEPENDS ON PHASE OF AUX WRT MAIN DATA CHANNELS SYS BLK SYS BLK * AUX, MAIN DATA INPUT FROM TAPE ,,,,,,, ,, ,,,,,,, ,, ,,,,,,, ,, 3 0 0 1 2 3 1 2 3 0 0 1 2 3 1 2 3 0 1 2 3 01 0 1 2 3 0 1 2 3 01 2 3 0 1 2 3 0 1 2 3 0 1 2 MLB414 Fig.32 SYSINFO and AUX block delays in DPAP mode; audio and AUX separately recorded. May 1994 39 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth SNUM 0 1 0 1 2 1 2 3 2 3 0 3 0 1 0 1 2 1 2 3 2 3 0 3 0 1 0 1 2 1 2 3 2 3 0 1 2 1 2 3 2 AUX BLK 01 3 0 SYS BLK AUX, MAIN DATA OUTPUT TO TAPE 3 0 1 2 3 0 1 2 3 0 1 2 3 01 MBG405 Fig.33 SYSINFO and AUX block delays in DRAR mode. SNUM AUX BLK SYS BLK SYS BLK * MAIN DATA INPUT FROM TAPE AUX OUTPUT TO TAPE ,,,,, ,,,, ,,,,, ,,,,,,, ,,, ,, ,,,, ,,, ,,,, ,,, ,,, ,, ,,,, ,, ,,, ,, ,,, ,,,, ,, ,,, ,,,, ,,,,, 123 ,,,,, 0 ,,,,, 3 0 0 1 2 3 1 2 01 2 3 0 1 2 3 0 1 2 1 2 3 0 1 2 3 3 0 1 2 3 0 1 ,,,,,, 0123 ,,,,,, ,,,,,, 2 3 01 0 1 2 3 3 0 1 2 0 1 2 3 0 1 2 3 01 1 ,,,,,,0 0123 ,,,,,, ,,,,,, 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 ,,, 01 ,,, ,,, 1 2 MLB416 Fig.34 SYSINFO and AUX block delays in DPAR mode. May 1994 40 Philips Semiconductors Preliminary specification Drive processor for DCC systems Scratch pad RAM The SAA3323 provides the microcontroller with a scratch pad RAM that the microcontroller can use for whatever it likes. The size of the scratch pad depends upon the size and type of RAM used with the SAA3323. The locations in SAA3323 the scratch pad RAM may be written and read in 8 bit or 12 bit units. The RAM may be viewed as having up to 4 quarters, the availability of these quarters for the scratch pad RAM is given in Table 44. Table 44 Availability of RAM quarters for the scratch pad RAM. RTYPE TYPE OF RAM USED 1 0 0 0 1 1 1 Note 1. In RAM quarter YZ = 00, the scratch pad is arranged as 6 pages, where each page consists of 7 columns x 64 rows. The pages are numbered 0 to 5, the columns 1 to 7 and the rows 0 to 63. This gives a total of (6 x 7 x 64) 2688 locations. In each of the RAM quarters YZ = 01, 10 and 11 the scratch pad is arranged as 6 pages where each page consists of 8 columns x 448 rows. The pages are numbered 0 to 5, the columns 0 to 7 and the rows 0 to 447. This gives then a total of (6 x 8 x 448) 21504 locations per RAM quarter YZ. During communication with the scratch pad RAM, the RAM quarter YZ is chosen when sending the RDDRAC, RDWDRAC, WRDRAC or WRWDRAC commands to the TFE module. Use of the scratch pad RAM outside the specified ranges is not allowed and it may upset the operation of the SAA3323. As with SYSINFO and AUX transfers can occur at high speed at all times except the second half of time segment 0, that is when the status bit SLOWTFR is HIGH. When SLOWTFR is HIGH the microcontroller must poll the status bit RFBT to investigate when a transfer can occur. Two addressing modes are available for the scratch pad, namely random access and auto-increment. For random access mode the address of each location is sent by the microcontroller to the SAA3323 before each location transfer. For auto-increment mode the address of the first location is sent by the microcontroller before the first location transfer, auto-incrementing of the row occurs then for all transfers until the end of the column. The 8 bit transfers are initiated by the WRDRAC and RDDRAC commands, these transfers are each 1 byte per memory location, therefore the byte counter will increment after each byte transfer. The 12 bit transfers are initiated by the WRDRAC and RDDRAC commands, these transfers are each 2 bytes per memory location. The first byte contains the 4 Most Significant Bits (MSBs) of the memory location in its 4 Least Significant Bits (LSBs) positions. The other bit positions being `don't care'. The second byte contains the 8 LSBs of the memory location. The byte counter is incremented after the transfer of the second byte. The RACCNT and BYTCNT registers are used for addressing the scratch pad. For RAM quarter YZ = 00 the mapping of the scratch pad RAM address onto the RACCNT and BYTCNT registers is shown in Table 45. 0 0 0 1 0 1 1 DRAM 64K x 4 DRAM 256K x 4 SRAM 32K x 8 fast SRAM 128K x 8 fast SRAM (2x) 32K x 8 slow SRAM 128K x 8 slow 00 00, 01, 10 and 11 00 00, 01, 10 and 11 00 00 and 10 AVAILABLE RAM QUARTERS YZ(1) May 1994 41 Philips Semiconductors Preliminary specification Drive processor for DCC systems Table 45 Mapping of scratch pad RAM address for RAM quarter YZ = 00. REGISTER BIT Value 6 P2 5 P1 4 P0 RACCNT 3 C2 2 C1 1 C0 0 1 7 1 6 R6 5 R5 BYTCNT 4 R4 3 R3 2 SAA3323 1 R1 0 R0 R2 For The other three quarters of the RAM the mapping of the scratch pad RAM address onto the RACCNT and BYTCNT registers is shown in Table 46. Table 46 Mapping of scratch pad RAM address for RAM quarter YZ = 01, 10 and 11. REGISTER BIT Value Mode changes The possible mode changes for the TFE are shown in Table 47. Table 47 Mode changes. CURRENT MODE DPAP DRAR DPAR NEW MODE DPAP - yes yes DRAR yes - no DPAR yes no - 6 P2 5 P1 4 P0 RACCNT 3 C2 2 C1 1 C0 0 R8 7 R7 6 R6 5 R5 BYTCNT 4 R4 3 R3 2 R2 1 R1 0 R0 Mode change DRAR to DPAP This mode change occurs at the first end of time segment 0 after the TFE module receives the new setting. Writing of Main and AUX data stops immediately after the mode change.The time segment jumps back to logic 0, URDA goes HIGH and stays HIGH for 5 time segments (i.e. approximately 213.3 ms) after which it goes LOW, as shown in Fig.37. Mode change DPAR to DPAP This mode change occurs at the first end of time segment 0 after the TFE module receives the new setting. The writing of AUX data to tape stops immediately after the mode change. The first AUX read from tape can be expected during the following time segment 0 or 1 (i.e. approximately 128 to 170.67 ms after the mode change), as shown in Fig.38. TIMING FOR SAA3323 MODE CHANGES Mode change DPAP to DRAR This mode change occurs at the end of the time segment in which the TFE module receives the new settings. Writing of the first Main and AUX data to tape starts at the start of the time segment 1 which occurs 2 `end of time segment 3' s after the mode change. The delay to writing to tape is approximately 222 ms, as shown in Fig.35. If `seamless appending' is required the new settings should be sent to the TFE module during time segment 2. Mode change DPAP to search This mode change occurs almost instantaneously, program the digital equalizer module in SAA3323 to go to search mode, then program the interrupt mask register to select the required type of interrupt. Mode change DPAP to DPAR This mode change occurs at the first end of time segment 2 after the TFE module receives the new settings. Output of AUX to tape begins at the start of the following time segment 1, (i.e. approximately 85.3 ms after the mode change), as shown in Fig.36. Mode change search to DPAP This mode change occurs almost instantaneously, program the interrupt mask register to disable interrupts program the digital equalizer module of SAA3323 to go to normal mode. A re-synchronization will most likely occur when as result of the data being read from tape, thus causing URDA to go HIGH. May 1994 42 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 andbook, halfpage SNUM 01 230 1 2 3 0 1 2 handbook, halfpage SNUM 1 2 3 01 DPAR 2 30 1 2 MODE NEW MODE DPAP DRAR DRAR MODE NEW MODE DPAP DPAR AUXILIARY, MAIN TAPE OUT 222 ms MEA707 - 2 AUXILIARY TAPE OUT 85.3 ms MEA708 - 2 Fig.35 Mode change to DRAR. Fig.36 Mode change to DPAR. handbook, halfpage SNUM 1 2 3 00 1 23 0 1 handbook, halfpage SNUM MODE 1 2 3 0 1 2 3 0 1 2 MODE NEW MODE DRAR DPAP DPAP DPAR DPAP DPAP NEW MODE URDA 213.3 ms MEA709 - 1 AUXILIARY TAPE OUT AUXILIARY TO MICROCONTROLLER 128 ms 170.66 ms MEA710 - 2 Fig.37 Mode change from DRAR. Fig.38 Mode change from DPAR. May 1994 43 Philips Semiconductors Preliminary specification Drive processor for DCC systems LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II VO IO IDD ISS Ptot Tstg Tamb Ves1 Ves2 Notes 1. The input voltage must not exceed maximum supply voltage unless otherwise specified. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. DC CHARACTERISTICS VDD = 2.7 to 3.6 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supply VDD IDD supply voltage supply current digital plus analog; see Fig.39 inputs with internal pull-down to VSS; all other inputs to VSS or VDD Inputs CLK24, L3CLK, L3MODE, PINI, SLEEP and SBMCLK VIL VIH II LOW level input voltage HIGH level input voltage input current VI = 0 V to VDD; Tamb = 25 C - 0.7VDD -10 - - - 2.7 - - tbf 28.1 - 3.6 - 100 PARAMETER CONDITIONS MIN. TYP. PARAMETER supply voltage input voltage input current output voltage output current supply current supply current total power dissipation storage temperature operating ambient temperature electrostatic handling electrostatic handling note 2 note 3 note 1 CONDITIONS 2.7 -0.5 -10 tbf -20 - -100 - -55 -40 -2000 -200 MIN. SAA3323 MAX. 3.6 VDD + 0.5 +10 tbf +20 100 - 500 +150 +85 +2000 +200 V V UNIT mA V mA mA mA mW C C V V MAX. UNIT V mA A 0.3VDD - +10 V V A Inputs TEST0, TEST1 and TEST2 VIL VIH II LOW level input voltage HIGH level input voltage input current - 0.7VDD VI = VDD; Tamb = 25 C 25 - - - 0.3VDD - 400 V V A May 1994 44 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SYMBOL Input RESET VtLH VtHL Vhys PARAMETER CONDITIONS - MIN. - - TYP. MAX. UNIT positive-going threshold negative-going threshold hysteresis (VtLH to VtHL) 0.8VDD - - V V V 0.2VDD - 0.3VDD Outputs AZCHK, CHTST1, CHTST2, ERCOSTAT, L3INT, L3REF, MCLK, PINO3, RDSYNC, SBDIR, SBEF, URDA, TCLOCK and WDATA VOH VOL VOH VOL VOH VOL IOZ HIGH level output voltage LOW level output voltage IO = 1 mA IO = -1 mA IO = 2 mA IO = -2 mA IO = 1 mA IO = -1 mA VI = 0 V to VDD; Tamb = 25 C IO = 1 mA IO = -1 mA outputs in 3-state outputs in 3-state VI = 0 V to VDD; Tamb = 25 C IO = 2 mA IO = -2 mA outputs in 3-state outputs in 3-state VI = 0 V to VDD; Tamb = 25 C IO = 4 mA IO = -4 mA outputs in 3-state outputs in 3-state VI = 0 V to VDD; Tamb = 25 C VDD - 0.5 - VDD - 0.5 - VDD - 0.5 - -10 - - - - - - - - 0.4 - 0.4 - 0.4 +10 V V Outputs A0 to A8, A9/CAS, A10/RAS, OEN and WEN HIGH level output voltage LOW level output voltage V V Outputs SPEED and PINO2 HIGH level output voltage LOW level output voltage 3-state leakage current V V A Inputs/outputs SBCL, SBDA and SBWS VOH VOL VIL VIH IOZ HIGH level output voltage LOW level output voltage LOW level input voltage HIGH level input voltage 3-state leakage current VDD - 0.5 - - 0.7VDD -10 - - - - - - 0.4 0.3VDD - +10 V V V V A Inputs/outputs A11 to A16 and L3DATA VOH VOL VIL VIH IOZ HIGH level output voltage LOW level output voltage LOW level input voltage HIGH level input voltage 3-state leakage current VDD - 0.5 - - 0.7VDD -10 - - - - - - 0.4 0.3VDD - +10 V V V V A Inputs/outputs D0 to D7 VOH VOL VIL VIH IOZ HIGH level output voltage LOW level output voltage LOW level input voltage HIGH level input voltage 3-state leakage current VDD - 0.5 - - 2 -10 - - - - - - 0.4 0.8 - +10 V V V V A May 1994 45 Philips Semiconductors Preliminary specification Drive processor for DCC systems Average current consumption SAA3323 60 I DD (mA) max 40 typ MLB778 min 20 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 Fig.39 Average current consumption. AC CHARACTERISTICS VDD = 2.7 to 3.6 V; Tamb = -40 to +85 C; CL = 10 pF on all outputs; see Fig.40; unless otherwise specified. SYMBOL Clock inputs CI CLK24 fCLK24 t24L t24H SBMCLK fSBMCLK tSCL tSCH clock frequency pulse width LOW pulse width HIGH 30 30 6.144 - - 12.5 - - MHz ns ns clock frequency pulse width LOW pulse width HIGH 24 12 12 24.576 - - 25 - - MHz ns ns input capacitance - - 10 pF PARAMETER CONDITIONS MIN. TYP. MAX. UNIT May 1994 46 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SYMBOL Clock output MCLK CL td fMCLK tMCL tMCH tpd Inputs CI tsu th PINI tsu th Outputs CL A0 TO A8 tpd PARAMETER CONDITIONS - - MIN. - 20 TYP. MAX. UNIT load capacitance delay time from SLEEP HIGH to SLEEP active clock frequency MCLK pulse width LOW MCLK pulse width HIGH propagation delay time from rising edge of CLK24 20 - 6.25 - - 65 pF ns MHz ns ns ns 6.144 50 50 - - - - input capacitance - 35 0 - - - - - - - 10 - - - - pF L3CLK, L3MODE AND RESET set-up time to rising edge of MCLK hold time from rising edge of MCLK ns ns set-up time to rising edge of MCLK hold time from rising edge of MCLK 60 0 - - ns ns load capacitance 20 pF propagation delay time from falling edge of CLK24 50 ns A9/CAS, A10/RAS AND OEN tpd td WEN tpd propagation delay time from falling edge of CLK24 from falling edge of WEN to rising edge of CLK24 td delay time from SLEEP HIGH to SLEEP active long write pulse mode - - - - - 20 50 50 - ns ns ns propagation delay time from falling edge of CLK24 delay time from SLEEP HIGH to SLEEP active - - - 20 50 - ns ns AZCHK, CHTST1, CHTST2, L3INT, PINO3, RDSYNC, SBEF AND WDATA tpd propagation delay time from rising edge of MCLK - - 45 ns ERCOSTAT, L3REF, SBDIR, SPEED, PINO2, URDA AND TCLOK tpd propagation delay time from rising edge of MCLK - - 55 ns May 1994 47 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SYMBOL Inputs/outputs CI CL A11 TO A16 td tpd D0 TO D3 td tsu th tpd PARAMETER CONDITIONS - - - - MIN. - - 25 - TYP. MAX. UNIT input capacitance load capacitance 10 20 - 55 pF pF delay time from SLEEP HIGH to SLEEP active propagation delay time from falling edge of CLK24 ns ns delay time from SLEEP HIGH to SLEEP active set-up time to falling edge of CLK24 hold time from falling edge of CLK24 propagation delay time from falling edge of CLK24 from rising edge of CLK24 - 5 15 - early write mode - - 5 15 - early write mode - - 35 0 - - - 40 0 - - 20 - - - - 25 - - - - 25 - - - - 25 - - - - - - - 50 50 - - - 50 50 - - - 50 45 - - - 60 55 ns ns ns ns ns D4 TO D7 td tsu th tpd delay time from SLEEP HIGH to SLEEP active set-up time to falling edge of CLK24 hold time from falling edge of CLK24 propagation delay time from falling edge of CLK24 from rising edge of CLK24 L3DATA td tsu th tpd delay time from SLEEP HIGH to SLEEP active set-up time to rising edge of MCLK hold time from rising edge of MCLK propagation delay time from rising edge of MCLK from L3MODE SBCL AND SBWS td tsu th tpd delay time from SLEEP HIGH to SLEEP active set-up time to rising edge of MCLK hold time from rising edge of MCLK propagation delay time from rising edge of SBMCLK from rising edge of MCLK (3-state control) May 1994 48 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SYMBOL SBDA td tsu th tpd PARAMETER CONDITIONS - 35 0 - MIN. TYP. - - - 55 MAX. UNIT delay time from SLEEP HIGH to SLEEP active set-up time to rising edge of MCLK hold time from rising edge of MCLK propagation delay time from rising edge of MCLK 25 - - - ns ns ns ns handbook, full pagewidth t 24H V IH V t su1 t h1 t 24L IL CLK24 IN1 t d1 OUT1 t MCL MCLK t su2 IN2 td OUT2 t SCL t d5 OUT3 MGB407 V IH t d2 V IL VOH VOL t pd t MCH t d4 VOH t h2 VOL V IH V IL VOH VOL V IH t SCH V IL VOH VOL SBMCLK Fig.40 Timing for AC characteristics. May 1994 49 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 ADC CHARACTERISTICS VDD = 2.7 to 3.6 V; Tamb = -40 to +85 C; CL = 10 pF on TCLOCK output; see Fig.41; unless otherwise specified. SYMBOL Vref(p) Vref(n) Vref Zi CI II DNL PARAMETER AC RDMUX ADC resolution positive reference voltage negative reference voltage Vref(p) to Vref(n) input impedance input capacitance (RDMUX) input current differential non-linearity -20 dB (FS); 100 to 500 kHz Vref(p) to Vref(n) Vref(n) to VSS CONDITIONS - - 0 2.0 700 - - - - 24 MIN. 8 - - - 1200 650 - - - - TYP. - VDD - 0.5 - - 1500 - 15 90 0.99 - MAX. V V V pF A LSB dB UNIT bits S/(THD+N) signal-to-total harmonic distortion plus noise ratio Timing Tcy td1 tsu th cycle time of CLK24 TCLOCK delay time from rising edge of CLK24 RDMUX set-up time to falling edge of CLK24 RDMUX hold time from falling edge of CLK24 40 CL = 10 pF Zsource < 150 - 60 40 - - - - - 80 - - ns ns ns ns handbook, full pagewidth t d1 V IH V IL V OH VOL CLK24 t d2 TCLOCK t d3 CLK ADC t su RDMUX t d4 TESTBUS DATA SAMPLE(1-3) DATA SAMPLE(1-2) MGB408 Tcy th SAMPLE(1) V IH V IL Fig.41 ADC timing. May 1994 50 Philips Semiconductors Preliminary specification Drive processor for DCC systems DAC CHARACTERISTICS VDD = 2.7 to 3.6 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Vo PARAMETER DIGEYE/ANAEYE resolution ANAEYE output voltage ZL > 1 M CONDITIONS - - MIN. 6 TYP. - (VDD - 1.1) - to VDD SAA3323 MAX. V UNIT bits May 1994 51 Philips Semiconductors Preliminary specification Drive processor for DCC systems PACKAGE OUTLINES SAA3323 handbook, full pagewidth seating plane 0.1 S S 14.3 13.7 80 1 pin 1 index 0.5 61 1.45 60 1.05 (4x) B 0.25 0.13 20 21 0.5 0.25 0.13 12.1 11.9 0.15 M A 40 1.45 (4x) 1.05 A X 41 0.15 M B 12.1 14.3 11.9 13.7 1.5 1.3 0.70 0.58 0.16 0.04 0.18 0.12 1.7 1.5 MBB947 detail X 0.7 0.3 0 to 4 o Dimensions in mm. Fig.42 Plastic thin quad flatpack; 80 leads; body 12 x 12 x 1.4 mm (SOT315-1; TQFP80). May 1994 52 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 handbook, full pagewidth seating plane 0.10 S 18.2 17.6 S B 65 64 80 1 pin 1 index 1.0 (4x) 0.6 0.8 0.45 0.30 41 25 0.45 0.30 14.1 13.9 40 1.2 (4x) 0.8 A 24 0.20 M A 0.20 M B 20.1 24.2 19.9 23.6 0.8 X 2.90 2.65 1.4 1.2 0.25 0.05 0.25 0.14 3.2 2.7 1.0 0.6 detail X 0 to 7 o MSA394 - 1 Dimensions in mm. Fig.43 Plastic quad flatpack; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height (SOT318-2; QFP80). May 1994 53 Philips Semiconductors Preliminary specification Drive processor for DCC systems SOLDERING Plastic quad flatpacks BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be SAA3323 applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. May 1994 54 Philips Semiconductors Preliminary specification Drive processor for DCC systems DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA3323 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V. May 1994 55 Philips Semiconductors - a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2327, Fax. (011)829-1849 Canada: INTEGRATED CIRCUITS: Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave, SCARBOROUGH, ONTARIO, M1B 1M8, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H., P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., Components Div., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Components Dept, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS COMPONENTS S.r.l., Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.3302, Fax. (02)6752 3300. Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)14163160/4163333, Fax. (01)14163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., Components Division, 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD31 (c) Philips Electronics N.V. 1994 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 513061/1500/01/pp56 Document order number: Date of release: May 1994 9397 732 30011 Philips Semiconductors |
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